The present invention relates generally to memory devices, and more particularly to data input and output circuits capable of supporting multi (e.g., double) data rate operation and a number of timing schemes.
Memory devices are integral to computer systems, and to many electronic circuits. Continuous improvements in the operating speed and computing power of central processing units (CPUs) enable operation of an ever-greater variety of applications, many of which require larger and faster memories. Larger memories are characterized by having more memory cells to store more bits of data. Faster memories can be provided by reducing the time necessary for each read and write cycle and by allowing for access of multiple data bits on each clock cycle.
Memory devices can be designed to support a number of operating modes such as a single data rate (SDR) and a double data rate (DDR) mode. In the SDR mode, one data bit is accessed (i.e., written to or retrieved from the memory device) for each device input/output (I/O) pin and on each active clock cycle. In the DDR mode, two data bits are accessed for each device I/O pin on each active clock cycle. The memory devices may further be designed to support other operating modes such as a block write mode in which a block of data bits is concurrently written to memory.
Larger memory devices typically include many device I/O pins to support concurrent access of many data bits. The memory cells within a memory device are coupled to the I/O pins through a structure of interconnections. As the number of I/O pins increases and the number of memory cells in the memory device grows, the interconnection structure also grows in complexity. Moreover, the data input and output circuits to interface the memory cells to the device I/O pins become more complicated, particularly if the memory device is required to support a number of operating modes.
Memory devices are also designed to meet various timing specifications. When the operating speed is slow, these timing specifications can be more easily satisfied because of the longer clock period. However, as the operating speed increases, it becomes more challenging to meet these timing requirements. More complicated timing circuits are typically required to generate triggering signals for synchronous circuits within the memory device to ensure conformance with the input and output timing specifications.
As can be seen, data input and output circuits that can support multi data rate operation and a number of different timing schemes are highly desirable.